使用晶圆级方法评估设备可靠性

ABSTRACT:

This paper demonstrates the viability of wafer-levelmethods as a means of evaluating device reliability usingspecial reliability test structures and process controlmonitors (PCM). The results presented illustrate howthis methodology can be employed to rapidly andeffectively assess the impact of process or materialchangeson over-all reliability.Thewafer-levelmethodology provides a quick feedback loop for themanufacturing group enhancing theirability tocontinuously improve on their processes.

Introduction:

In the compoundsemiconductormanufacturingenvironment making changes to an existing process ormaterial to further enhance the performance of devices iscommonplace. This fluidity necessitates a methodology thatquickly evaluates the effects of these changes onfundamental process reliability.The method of wafer-level accelerated lifetesting allowsreliability studies in a straightforward and eflicient manner.It can be accomplished on individual devices on a singlewafer or on multiple devices on entire wafers. The wafer-level aspect of stressing provides a spatial map of reliabilityfor a wafer and a single wafer can provide enough samplesWithout the need for hundreds of devices and long-termlifetesting at lower temperatures this technique allows for arapid and efficient means of evaluating device reliability.Packaging considerations are eliminated by doing thesestudies on wafer. TThis makes it easier to observe devices anddo root cause analysis of the failure mechanism.The results from wafer-level lifetesting provide a first-hand look at the consequences a process or material changeaffects on the reliability of devices. Wafer-level studiesaugment existing HTOL procedures and protocols. Based onthe results, a decision to expend additional resources to docomplete reliability studies can be made.

The Nature of Wafer-level Reliability Studies

The wafer-level approach to reliability studies atTriQuint Semiconductor builds on an extensive history ofreliability studies in general A crucial aspect of utilizingwafer-level reliability studies is the ability to interpret theresults against a well-defined baseline. The historical contextis built on data obtained from more traditional methods suchas HTOL. This knowledge helps define key elements of wafer-levellifetestingamong themselectingwhichparameters matter, what failure criteria is acceptable andwhat wafer-level stresses are appropriate for these studies.Another aspect of the wafer-level methodology is theuse of standard test vehicles. At TriQuint Semiconductorthe standard test vehicle includes a unique reliability testmask populated by proprietary test structures as well asprocess controlmonitor (PCM) structures. These teststructures allow wider latitudes of flexibility and efficiencythat is not possible when employing specific circuitry.The wafer-level methodology is most powerful whenevaluating a process or material change against anestablished standard. This entails a careful measurement ofkey device parameters before and after wafer-level stresscomparing any notable shifts between the experimental andcontrol cells. In general, the method of wafer-levellifetesting is a measure of relative reliability between a newprocess or material system and an established process ormaterial system.

Methodology:

Wafer reliability testing involves two types of agingWafer-Scale Reliability ( WSR) refers to reliability testingperformed simultaneously on all structures contained on awhole wafer.All structures of interested are measuredbefore the stress and once again after the stress. WSR agingis particularly applicable for whole-wafer stresses such asautoclave and temperature cycling. Wafer-Level Reliability(WLR) refers to aging tests applied to one structure at atime. An individual structure is measured and stressed andre-measured.Then, the next structure can be measuredunder the same stress or with different stress, so thatdistribution parameters and/or acceleration factors can bedetermined, and spatially mapped, within an individualwafer. WLR aging is particularly applicable for metal orresistor electromigration evaluations and capacitor TimeDependent Dielectric Breakdown (TDDB) studies.

A.WAFER-SCALE BAKE

A first-pass evaluation of device reliability involves asimple wafer-bake of wafers at 275°C. Key deviceparameters such as pinch-off, channel current, gate diodeturn-on, breakdown voltage andgate leakage current aremeasured prior to and after the bake. This is done on wholewafers containing numerous devices. The bake is done in anambient-air oven for 168 hours. This temperature is designedto cause a 20% decrease in channel current in a MESFETdevice as determined in a previous study.

B.WAFERSCALE AUTOCLAVE

Wafer-scale autoclave is a rudimentary evaluation ofdevice moisture sensitivity. Following JEDEC StandardNumber 22.Method A102. whole wafers are autoclaved at121°C with 100% relative humidity for 96-hours. Like waferbake, key device parameters are measured before and aftermoisture exposure.

C.WAFER-LEVEL ACCELERATED LIFETESTING

A more in-depth characterization of device reliabilityincludes a determination of the activation energy of a deviceunder test (DUT). In this study, this is determined bythermally stressing individual DUTs using a speciallydesigned reliability test structure. The test structure includesan on-wafer heating element that surrounds the DUT. Theheating element utilizes a thin film resistor (TFR). Using thistest structure, heating is localized around the DUT.