晶圆级键合工艺

Abstract 

The objective of this study was to develop a fullyintegrated process for wafer level MEMS packagingutilizingPoly-Si through silicon via (TSV) capped MEMS devices.First, interconnection metallurgy and Solid Liquid Interdiffusion(SLID) bonding process was optimized. Then sc. “vias beforebonding” capping process and contact metallizations for Poly-SiTSVs were developed.Finally, the process integration wasdemonstrated by using piezoelectrically driven MEMS actuatorsHowever, several design and manufacturing related challengeswere observed and detailed failure analysis were carried outto resolve these problems.

I.INTRODUCTION

Functional structures utilized in Micro Electro MechanicalSystems (MEMS) have to be electrically connected and oftenencapsulated. Wafer level Solid LiquidhermeticallyInterdiffusion (SLID) bonding, also known as Transient Liquid-Phase (TLP) bonding, a sub-category of the metal bonding, isbecoming an increasingly attractive method for industrialusage[1-5]. The main advantages of SLID are the possibility toutilize a low melting point metal to reduce the bondingtemperatures, a significant reduction of the bonding footprintthat is required for metallic bonding as well as the possibility toachieve simultaneously vertical electrical interconnections whenutilizing through silicon vias (TSVs).

Out of the several different material options demonstrated.Ag-In [6-8], Au-In 2, 9-14], Cu-In [15], Ag-Sn [16,17], Ni-Sn[2, 3,18-20], Au-Sn [21-28] and Cu-Sn [5, 29-38], Au-Sn andCu-Sn based metallurgies are the most commonly utilized inSLID systems. In general, the formation of the bond in the SLIDprocess occurs in four consecutive stages: melting, dissolutionintermetallic compounds (IMCs) formation that leads tosolidificationhomogenization of theisothermalandinterconnection structure. Immediately after the melting of thelow melting temperature metal (i.e. Sn or In) rapid dissolution of the high melting temperature metal (i.e. Ag, Au, Cu or Ni)occurs. The dissolution rate is system dependent and is mainlyaffected by the solubility of the high melting temperature metalto the liquid. Once local supersaturation of the low-meltingmaterial occurs, subsequent isothermal solidification of theIMCs takes place. Finally, the bond is homogenized via solid.state reactions.

The objective is to study MEMS wafer level packaging witha fully integrated SLID bonding process for Poly-SiTSV cappedMEMS devices. The development consists of studies for theprocess sequence and deposition methods required for theprocessing of sensitive MEMS structures and multi-stack andmulti-material interconnection layers. A prime example of thisis the deposition of contact metallizations and bonding materialsthat limits the design features and process integration optionsSensitive MEMS structures must be protected from thesedeposition processes, particularly when harsh chemical orelectrochemical methods are used and how the bondingmaterials are protected during MEMS structure release. Inaddition, the integration of TSVs, TSV contact metallizationsand the design and manufacturing ofthe 3D network ofelectricalpaths for the functional structures are studied. Finally, a generalrefection is made on the wafer-level bonding as a whole, how theconsecutive processing steps can be optimized for optimalfunctionality and reliability. This requires a thoroughunderstanding of the structures and the underlying materialcompatibility, global and local thermo-mechanical stresses andvolumetric changes as materials evolve over a processing anooperational lifetime. In this paper the design, process andreliability assessment of sc.“vias before bonding cappingprocess will be carried out in three consecutive stages. First, theselection of bonding metallurgy is made and the mechanicalreliability will be assessed. Second, the contact metallizationstructures, Poly-Si TSV manufacturing process flow as well ascap wafer backside processes are developed frommanufacturability and reliability viewpoints. Finally, processintegration for Poly-Si TSV capped MEMS wil bedemonstrated.

I.MATERIALS AND METHODS

Standard double side polished 150 and 200 mm siliconwafers (thickness 400 um) were used as device and cap wafersBoth wafer types were <100> with p-doping and weremanufactured by Okmetic. For the first phase metallurgicalstudies a 40 nm TiW layer was sputtered as an adhesion layerbetween the silicon and the seed layer. A 100 nm thick gold orcopper seed layer was sputtered to both wafers. The seal ringgeometry was rounded-corner rectangle with dimensions of1,576 um x 783 um and the width of the ring was 60 um. 4 umand 6 um thick gold and copper layers were electroplated. Thena 2 um thick tin layer was electroplated on top of the Au or Culayers. In order to study the effect of an additional nickel contactmetallization between TiW and electrochemical Au a 200 nmthick nickel film was sputtered prior to seed layer deposition.More detailed description can be found from [39]. EVG 610bond aligner and EVG 510 bonder were used in the bondingtests. For the electrical bonding tests,400um p-doped DSPdummy MEMS wafers were bonded onto 625um TSV capwafers from Okmetic. The dummy MEMS wafers had a 500nmthermal oxide insulation, the cap wafers Poly-Si filled TSVswith an oxide liner. TS Vs were arranged into 30 TSV matrixeswhere the TSVs had a 250um pitch. 2500um die size was usedin the electrical test layout.