快速扩大 GaAs晶圆背面处理的挑战

ABSTRACT

The dramatic increase in demand for GaAs basedpHEMT and HBT devices has required the expansion ofwafer FAB capacity. One of the major challenges inexpanding FAB capacity lies in the back-side processarea. Historically, most GaAs back-side wafer processsteps had been very labor intensive since there was notmuch available in manufacturing equipment to supportthese steps. Yield had often depended on the skill ofexperienced technicians. A number of back-side processsteps have recently been changed and/or automated inorder to dramatically increase throughput and improveyield. GaAs FAB process engineers are working closelywith equipment vendors to further optimize and qualifynew equipment for the back-side area.

INTRODUCTION

A description of the various steps involved in back-sideprocessing for GaAs wafers is given below. Figure 1 shows across-sectional view of the major steps as the GaAs waferTheundergoes backside processing with via-holes.following steps are performed after completion of final front-side DC electrical test.

1.For back-side via-hole processing, the wafers are mountedonto flat carriers with the front-sides adjacent to athermoplastic mounting medium or high temperature wax.The most widely used flat carriers are fabricated fromsapphire, which is thermally compat ible with GaAs, resistantto most wet chemical etch solutions, and can be machined toan optically flat surface. For GaAs devices that do notrequire backside vias or front-side airbridges, back-grinding(BG) tape° or a thick photoresist layer can be applied toprotect the wafer front-sides during thinning operations. 2. The wafers are thinned to the desired thickness range by51using a combination of the following techniques: grinding111ll , and/or wet immersion5, 12, 13 polishinglappingor spray6，10etchingFor high volume applications rough grinding isusually employed followed by polishing, spray etching, or animmersion etch to remove several ums of residual grinding.5, 10 Rough grinding followed by slower speed finedamage.grinding and immersion or spray etch to remove a few ums ofresidual damage is also used 1, 6-93. For GaAs wafers that do not require back-side vias orfront-side airbridges, the back-grinding (BG) tape can be removed with a wafer de-taping system'or the protectphotoresist can be wet stripped. For GaAs wafers thinnedusing BG tape, ultra-violet (UV) sensitive tape is utilizedsince the UV exposure before peeling reduces the tapeadhesion strength by at least an order of magnitude. UV BGis extensively used for very thin silicon wafer Smart cardapplications6Most automatic wafer de-taping systems offera UV exposure module option. The UV BG de-tape step canbe done after the dice tape frame mount step, so that thethinned wafer is continuously supported with tape from thegrind through dice steps. Wafer tape system vendors aredeveloping new cassette to cassette tools that combine these14 The process flow for non-via devices continuestwo steps."at step 8 belowFor via-hole processing, the via mask isdefined on the backside wafer surfaces using a thickphotoresist layer and either an infrared (IR) contact or dualside image mask aligner.' After the photoresist masks arehardened with a post-bake, the via holes are etched usingeither reactive ion etch (RIE)15-23or inductively coupledplasma (ICP)2426Batch RIE systems, which can handle upto four 100 mm diameter wafers per run, have been widelyused. However, single wafer ICP is being employed as GaAs26FABs convert to processing 150 mm diameter wafers.

4. The thick photoresist mask is stripped from the back-sidewafer surfaces with a stripper solution followed by exposureDependingto a high oxygen content plasma environment."Depending on the aggressiveness of the photoresist cross-linking and thevia hole etch conditions, the stripper solution may need to beeither sprayed onto the wafer backside surfaces or the wafersneed to be immersed and agitated in heated stripper solution.However, the immersion technique can result in someleaching of the exposed mounting medium at the thinnedwafer / carrier sandwich perimeter. If a wet spray striptechnique cannot be utilized, then a high oxygen content RIEcan be used to totally remove the residual organics from thebackside wafer surfaces prior to seed layer deposition.