用于连接CMOS IC的湿式蚀刻硅互换器

In this paper, a novel wet etched silicon interposer for optical interconnection  applications has been proposed and fabricated. The interposer concept is conceived to  include, via flip chip bonding, both CMOS ICs and optoelectronic dies to allow close  proximity of electronics (drivers, TIAs) to photonics (VCSELs, PDs). The fabrication  steps are developed to realize silicon recessed areas, to fit the semi-conductor circuitry,  and openings to fit mechanical optical interface (MOI). Two steps of silicon anisotropic  wet etch are performed to define these areas. The metal traces for electrical connection  are designed to match the impedance for signal transmission and are lithographically  defined. The obtained silicon interposer is shown and the process challenges discussed.

In the past few decades, the performance of data centres (DC) and High-performance  computing (HPC) has been growing with an exponential rate. To sustain this growth rate, it is projected that existing electrical interconnects in standard 19” width rack  equipment connecting ASIC and pluggable transceivers on the front panel will be  replaced by mid-board-optics (MBO) due to the front panel bandwidth density limits .  The footprint and the cost of the key modules (transmitter and receiver) are the main  limitations, mostly due to the complex packaging. At present, the vertical-cavity surfaceemitting lasers (VCSELs) and surface normal photodetectors (PDs) arrays are the most  promising photonic technology to realize transceivers. During the fabrication, the  components are packaged on printed circuit boards (PCB), where dense integration is  complicated and costly to assemble and fabricate. Besides, point-to-point wire bonding is  employed to make the connections between the CMOS IC and optoelectronic dies, which  increases the cost and suffers from limited RF performance .

In this paper, we take advantages of silicon wafer scale process, and fabricate a novel silicon interposer by wet etching and double side-etching. The patterned silicon interposer is then gold plated to link the dense interconnections between the FR-4 PCB and the  silicon ICs. Also, funnel-shaped TSV are realized to couple the laser light from a VCSEL to the mechanical optical interface (MOI) and Multiple-Fiber Push-On/Pull-off  (MTP/MPO) connector.

We propose a scheme to assemble the components scalable to wafer level  packaging/assembly, which can provide the high performance and cheap transmitter module. As shown in Fig.1, the silicon interposer has been designed to assemble the  CMOS driver, VCSEL and MOI. The chips, VCSELs and driver, are embedded in the  silicon interposer. Lithographically defined metal traces, impedance matched for high  speed transmission, are defined at the front-side of the interposer. At the backside of the  same interposer the MOI are placed after opening the squared TSV to get light from the  12 VCSEL channel.

Fig1

The 2nd lithography is carried out on the already etched structure, after sputtering the  seed layer for plating. The thick positive chemically amplified photoresist AZ® 40XT is  employed for electro-plating. As shown in the Fig. 4(a), the photoresist is smoothly  continuous after exposure and development of the photoresist: the light traces are the  opening in the photoresist. A one micron thick layer of gold is then plated. Fig. 4b & c,  shows the fan-out differential traces and short ground signal ground (GSG) traces between CMOS and VCSEL array after removing the seed layer.