The Through Silicon Via (TSV) is expected to be the future of 3-D chip stacking technology for electronic devices. The structure of the TSV interconnect is developed by first etching deep vias into the surface of a wafer, and later filling those vias with a desired metal. Currently, copper based TSVs are the most cost effective mass producible TSVs. Vias filled with copper provide the interconnect ―through‖ the wafer, once both the top and the bottom of the vias are exposed. This provides a solid robust interconnect isolated and protected by the wafer. It also provides the interconnect using much less volume, while reducing the need for a majority of the packaging associated with modern microelectronic packages. Copper based TSVs were produced in this work using two methods, the ADE method and the blind-via method. The ADE method introduces a unique process that is potentially compatible with post-microelectronic manufacturing. The fabricated TSVs from both methods were cross-sectioned for analysis, which revealed successful formation of solid copper TSVs.
I first would like to thank God, for without his support none of this would be possible. I would like to thank Dr. Robert N. Dean for his guidance, expertise, and support throughout my studies and this work. I would like to thank Dr. Thomas Baginski and Dr. Thaddeus Roppel for their support in joining my committee. I also would like to thank Charles Ellis and Michael Palmer for their knowledge and support in the lab. I would like to thank AEgis Technologies for funding the work and Eric Tuck and Derek Strembicke for their collaboration efforts in making this successful. I would like to thank Colin Stevens and Shakib Morshed for their help in the lab. I would also like to thank my professors and the department for their support. I finally would like to thank my family for their encouragement, love and support throughout my studies.
As the package size of modern microelectronics rapidly shrinks, Moore’s law begins to accurately describe the limitation on the amount of technology that can fit on an integrated circuit. The development of single electron transistors such as the SketchSET; however, have given us a glimpse towards the end of transistor scaling [1]. As the end of Moore’s law approaches, a more recent approach emerges, called ―More than Moore‖. This new trend attempts to improve systems by reducing the package size of devices. This ultimately delivers a higher component density. This transitions the electronic world from a classical multichip module, in which multiple chips were used for different functions, to a system on chip (SOC) model which integrates everything into a single chip. Production of such a chip, however, can be difficult with current conventional approaches.
One of the main limiting factors in package size comes from a chip’s interconnects. Modern technology heavily uses wire bonds, which may take little material volume but as a result of their use they waste much more 3-D space. This is because nothing can come in contact with them, forcing them to be spatially separated from the chip and each other. Additionally, they have to be electrically isolated using more material. The leading alternative to wire bonds is the utilization of Through-Silicon-Vias (TSVs). TSVs are interconnects that pass through a wafer or chip allowing for an electrical connection through the substrate. This technology is beginning to be commercially utilized in many different devices, and it shows a promising future in many prospective applications including cameras [2], video cameras , and DRAM .
Fig1
Mechanical drilling is the same for micro scale as it is in macro scale. It uses a bit which is smaller than the hole being drilled, and is made from a strong enough material to withstand the forces associated with drilling (i.e. cemented carbide)[17]. Mechanical drilling can have an aspect ratio >10, although the feature size must be greater than 300μm, and the roughness is considered ―average‖ [18]. The average sidewall roughness is due to the drill bit’s nonuniformity and possibly micro-deformations developed due to drilling forces/abrasion. Although, the aspect ratio and roughness may be workable into a TSV procedure, the feature size is too large to be commercially viable.
