As feature sizes continue to the 45nm and 32nm nodes, significant challenges will continue to arise in bothfront-end-of-line (FEOL) and back-end-of-line (BEOL) applications. The reduced thickness, as well as thereduced etch resistance, of the photoresist (PR) makes it nearly impossible to use the PR as both an imagingand a pattern transfer layer. This etch challenge has led device manufacturers and vendors to explore theuse of multi-layer (trilayer) stacks. Multilayer stacks are typically comprised of a thick via-filling organiclayer that will provide adequate etch resistance while etching into low-k and ultra-low-k dielectrics. Asilicon-containing layer is then applied on top of the via-filling layer, which will provide improvedimaging, as well as etch resistance for the organic layer. The PR is then applied on top to complete themultilayer stack. While many challenges have presented themselves in multilayer stacks, new challengessuch as rework and cleaning have arisen. As low-k and ultra-low-k dielectrics become more prevalent,traditional oxygen ashing processes for the removal of PR and anti-reflective coatings can cause damage tothe dielectric layer due to the chemical and physical structures of the materials involved. While someprocesses have been developed to replace damaged dielectric material during ashing and etching throughsilyation, alternate processes are being developed where entirely wet stripping processes can removemultilayer stacks. One advantage of an entirely wet removal process is that it can prevent damage causedby ashing or etching, and the wet stripper is developed so it does not attack the dielectric films. While anentirely wet removal process has potential advantages, it still must be proven that these processes canremove residues that are left after etch processes, sufficient removal of particles are obtained, and anymaterial loss of the dielectric layer meets the requirements of the customer and the InternationalTechnology Roadmap for Semiconductors (ITRS). Other challenges are presenting themselves, as manycustomers would like to move from batch-type wet rework or cleaning processes to single wafer toolprocesses.
As the semiconductor industry continues to design devices for the 45nm and 32nm nodes, the industry as awhole is also going through continuous change. Device manufacturers are constantly using new dielectricmaterials to lower the dielectric constant and improve device performance. With these new materials anddevices, new challenges present themselves that might have not been as important in the past. Oneimportant factor is that the new dielectric materials will not stand up to the older rework/strip processes thatmanufacturers are accustomed to using. Another factor is that devices that use advanced multilayermaterials cannot simply be removed by traditional oxygen ashing techniques since the hardmask layer hasinorganic components that are very similar to those in the dielectric. While these two factors will be verydevice and materials specific, the industry as a whole is also looking at moving away from batch type toolsfor rework/strip processes and moving to advanced single wafer processing tools. While devicemanufacturers decide on what type of processing techniques they will require for their devices, the industryis also aggressively looking to reduce both acceptable defect sizes and overall defect counts. The followingfigure shows how aggressive the 2005 ITRS is for both acceptable defect size and defect counts after boththe lithography cell and the cleaning process.
There are a variety of reasons that device manufacturers would need to remove bottom anti-reflectivecoating (BARC) and resist materials from their substrates. One of the leading reasons that a device wouldneed to have BARC and resist materials removed, or reworked, would be loss of critical dimension (CD)control. As feature sizes continue to shrink on devices, the CD must be accurately controlled on eachwafer, as well as from wafer to wafer. Another reason for rework would be an incorrect overlay where theplacement of the image does not line up with the underlying layers. A third reason for needing a reworkprocess would be defect control. These issues, as well as many others, can cause electrical shorts in thedevice and can lead to yield loss.
Now that some of the reasons have been identified for rework processes, decisions must be made withregards to which layers must be removed in multilayer systems. There can be a variety of potential ways torework multilayer stacks. The following diagram illustrates some of the potential ways to rework BARCand resist materials on multilayer stacks.
While there can be a variety of rework processes to choose from, this paper will focus on rework of thesilicon material only and of the PR plus the silicon material, and on the rework of the via-filling material ina separate step. The rework of the PR layer by itself is not discussed in this paper due to the significantamount of prior art in the industry regarding this process.
Fig1
After determining that the acidic-based removers that were tested would only remove the silicon materialand could attack silicon substrates, it was decided to move on to test the basic-based removers to see theirremoval efficiencies in single wafer tool type processes and in alternate removal processes. Set-up waferswere run first to determine the best two temperatures and times for the rework of the silicon material. Thetemperatures and times were determined by looking at thickness loss and total defect counts. Thefollowing graph shows total defect counts for the rework of the silicon material using Remover 3 at both50ºC and 60ºC.
Since Remover 3 was able to remove the silicon material from silicon wafers (without damaging the wafer)and produce low defect levels, an alternate removal process was tested in which the PR was also removedin conjunction with the silicon material. The same temperatures and times were used to see how adding thePR layer would affect defect counts.
