Abstract:
We demonstrate comprehensive numerical studies on a hybrid III-V/Si-based waveguide system, serving as a platform for efficient light coupling between an integrated III-V quantum dot emitter to an on-chip quantum photonic integrated circuit defined on a silicon substrate. We propose a platform consisting of a hybrid InP/Si waveguide and an InP-embedded InAs quantum dot, emitting at the telecom C-band near 1550 nm. The platform can be fabricated using existing semiconductor processing technologies. Our numerical studies reveal nearly 87% of the optical field transfer efficiency between geometrically-optimized InP/Si and Si waveguides, considering propagating field along a tapered geometry. The coupling efficiency of a directional dipole emission to the hybrid InP/Si waveguide is evaluated to ∼38%, which results in more than 33% of the total on-chip optical field transfer efficiency from the dipole to the Si waveguide. We also consider the off-chip outcoupling efficiency of the propagating photon field along the Si waveguide by examining the normal to the chip plane and in-plane outcoupling configurations. In the former case, the outcoupling amounts to ∼26% when using the circular Bragg grating outcoupler design. In the latter case, the efficiency reaches up to 8%. Finally, we conclude that the conceptual device’s performance is weakly susceptible to the transferred photon wavelength, offering a broadband operation within the 1.5-1.6 µm spectral range.
1. Introduction
Quantum photonic integrated circuits (qPICs) are functionalized based on the quantum nature of photons . They can find applications in new fascinating fields related to quantum information processing and computing , quantum communication , or quantum metrology . As in classical photonic integrated circuits (PICs), chip-scale integration is a crucial factor offering miniaturization and thus a small system footprint, scalability, mechanical stability, low energy as well as material consumption, and low manufacturing costs . To achieve full application capabilities, the qPIC requires integrating various passive and active optical components within a single wafer-scale platform allowing for non-classical light generation, photon routing, control over the whole qPIC elements, and detection at a single photon level, or light outcoupling to the external photonic environment . Many existing material approaches are currently considered for developing a genuinely functional qPIC, including major platforms like silicon-on-insulator (SOI), silica-on-insulator (SiO2OI), silicon nitride (Si3N4), silicon oxynitride, aluminum nitride (AlN), silicon carbide (SiC), lithium niobate (LN), diamond (C), polymers, tantalum pentoxide (Ta2O5), gallium arsenide (GaAs), or indium phosphide (InP) . Nevertheless, within all the mentioned, monolithic fabrication of a functional qPIC-based device is currently very challenging or impossible, routing towards hybridization of many different materials.
Silicon-on-insulator is a very attractive major material platform that can be used for the qPICs integration. It has been successfully utilized in classical PICs, offering advantages such as compatibility with mature complementary metal-oxide-semiconductor (CMOS) technologies, thus allowing for electronic control over the qPICs elements , providing high index contrast necessary for the light routing and assuring low-cost, maturity, and high processingyield. Within the Si platform, one can fabricate various monolithic components, including splitters , crossings, phase shifters, filters, electro-optical switches, waveguides , multiplexers , micro-ring resonators and photon detectors. Notably, the silicon platform offers ultralow losses for light routing within a chip supported by a high refractive index. For the scalability of quantum photonic devices, low photon losses within a chip are of primary importance, being the scalability limiting factor . However, the main hurdle is the lack of a compatible non-classical photon source. It seems that, as in the case of other material platforms, hybridization of a non-classical photon generator with the Si platform might be a challenging but necessary solution.
In the first part of the work, we investigate the transmission of the tapered hybridized InP/Si WG section, as the vision is to provide the highest coupling of InAs/InP QD-confined dipole emission to Si WG via maximized light transmission through the tapered geometry. It is realized by scanning an extensive parameter space of the taper geometry and then simulating the multimode propagation along the number of taper structures. Next, we evaluate a dipole, directional emission coupling to guided modes confined in a specified hybrid InP/Si WG using a centered dipole position, and as a function of cross-sectional displacements. Finally, we study the possibility of emission outcoupling from the Si WG to free space that simulates an interlink between the qPIC and the off-chip transmission channel, e.g., an optical fiber. Each component’s transmission/coupling efficiency is examined with respect to the transmitted photon wavelength in the range of 1.5-1.6 µm, which is important for the device tolerance related to the imperfection of the component’s fabrication process. All of the components communicating on-chip could compose an envisioned nanophotonic circuit for quantum information processing, as schematically demonstrated in Fig. 1.
Fig. 1. Concept of a nanophotonic circuit for quantum information processing utilizing InAs/InP quantum dot emitters embedded in hybrid InP/Si waveguides on a common SOI platform. A typical nanophotonic chip may consist of photon sources, couplers, splitters, ring resonators, and light outcoupling systems off the PIC towards in-plane or out-of-plane directions of the chip.
2. Method and model structure
The geometry of InP and Si WGs and a hybrid WG are modeled within the Lumerical 3D CAD environment. Although the model is rather conceptual, our main concern is to find a realistic and a consistent model with the well-established fabrication and processing steps. There are a few possible approaches to realize these structures, including (i) in-situ lithography, (ii) transfer printing, or the (iii) pick-and-place method . For each of these techniques, at least one challenge can be identified: (i) the complex equipment needed, (ii) the low fabrication precision, and (iii) the low process yield, respectively. On the other hand, direct wafer bonding followed by electron beam lithography (EBL) was successfully applied to fabricate GaAs/Si3N4 waveguides. The benefits of the bonding approach are a relatively low complexity that leads to much better scalability and high fabrication accuracy (<50 nm, as compared with ∼1 µm for transfer printing). Notably, the results of the presented geometry optimization are independent of the fabrication method, however, to prove the usability of our approach, we give the details of the proposed fabrication based on direct wafer bonding. It requires the integration of an epitaxially grown InP wafer containing an array of self-assembled InAs quantum dots with an SOI wafer and subsequent WGs processing. The processing would start with patterning Si waveguides and alignment marks in the top layer of the SOI wafer. The next step would be plasma-activated direct bonding of InP to the patterned SOI chip [50], followed by removal of the InP substrate. Then, uncovered alignment marks previously defined in the Si layer would be used as a reference for deterministic patterning of InP WGs with a QD emitter on top of Si WGs. The final pattern of hybrid WG would then be transferred to the InP layer by dry etching (using the interferometry-based metrology to control the etch rate or deposition of a thin oxide layer as an etch stop). The overview of the fabrication steps is demonstrated schematically in Fig. 2.
Fig. 2. The proposed fabrication workflow to realize a quantum photonic integrated circuit with heterogeneously integrated InAs/InP quantum dot system on a silicon-on-insulator (SOI) platform: a) preparation of InP wafer with quantum dots and SOI wafer with a define Si waveguide, b) molecular wafer bonding process of flipped InP wafer, c) wet chemical etching process to remove InP substrate, and d) dry etching to define InP waveguide upon Si waveguide.
We find that the main requirement for the hybrid InP/Si WG geometry, enabling confinement of the fundamental mode in the InP part, is that the Si part must be of a smaller width than the InP part. However, we expect the structure to be mechanically unstable, so the subsequent results would be considered for the opposite constraints of our conceptual design, i.e. a narrower and higher InP part is placed on top of a broader and thin Si part. The proposed fabrication method allows for achieving the hybrid InP/Si WG, as depicted in Fig. 3. It consists of three elements that can be used to develop a simple qPIC demonstrator operating at a single photon level using an embedded InAs/InP quantum emitter. The first element is a hybrid waveguide structure containing an InP WG (with a single InAs QD embedded) on top of a Si WG of different widths. The second element is a tapered structure in which both the InP and Si WGs have tapered geometries. In the case of the InP WG, the taper shrinks along the propagation direction of the mode, whereas the inverted taper geometry is used for the Si WG. Here, we consider only the case where the taper length of the InP WG is equal to or smaller than the taper length of the Si WG. Both tapers have a linear dependence on the width along the waveguide direction. The third component is the Si WG section, which is an extension of the Si WG taper end without the InP WG on top. This component is terminated by the outcoupler ring structure, which can be used to scatter the transferred light to the off-chip detection system, normal to the structure plane. Optionally, the side detection system can be used for the cleaved facet of the sample. In both cases, photon outcoupling can be realized using a microscope objective or a lensed optical fiber to enable high collection efficiencies.
Fig. 3. Elements of the integrated quantum photonic circuit with the integrated quantum dot in a hybrid InP-Si waveguide system: a) quantum dot coupled in waveguide, b) linear taper structure, and c) grating outcoupler. All of these elements are feasible by using the proposed fabrication method in Fig. 2.
3. Results
3.1. Light transmission from the InP to Si waveguide
In this section, we study the transmission efficiency of a propagating light field from the hybrid waveguide section, through the taper region, to the Si WG section. To simulate the light field generated by a single InAs quantum emitter embedded in the InP WG, we use a Gaussian beam source (waist radius of 0.50-0.55 µm is used depending on w1InP) providing directional propagation of the field along the waveguide. The directional propagation of the Gaussian beam along the waveguide simplifies and generalizes the problem of finding efficient taper structure. First, the source excites a multimode propagation similarly to a random set of electric dipoles, which is related to a position uncertainty inside the InP WG expected for random in-plane distribution of self-assembled QDs in the InAs layer, and to the vertical shift of the QD layer determined during the growth process. Second, the directionality of the Gaussian beam source allows one to evaluate the taper transmission efficiency T for half of symmetric bidirectional dipole coupling. Third, due to the not preferred order of refractive index contrast, i.e. nInP < nSi, the Gaussian beam is located in InP circumventing excitation of the fundamental mode confined in Si, favouring higher-order modes relevant for the QDs embedded in InP. In this approach a single-shot simulation for a given geometry of the taper structure provides reliable results instead of time and resources consuming single-dipole modelling, and then by a parameter scan of the taper geometry we can search for optimized system with a maximum efficiency of the light transfer from hybrid WG to Si WG in a more efficient way.
In Fig. 4(a), we demonstrate the distribution histogram of the evaluated transmission coefficient T. The statistics of the results show T above 60% for the vast majority (74.8% cases) of a relatively simple taper structure and for a coarse scan of the geometries. It indicates that the tolerance in processing such tapered WGs would be relatively high, requiring the fabrication precision on the order of a few tens of nanometers for the tapered InP and a few hundreds of nanometers for inversely tapered Si WGs, respectively. Thus, while electron-beam or deep-UV lithography should be used for fabricating InP WGs, the requirements for the fabrication of Si WGs are relaxed, and a simpler UV lithography technology could be employed.
Fig. 4. (a) Histogram of the transmission coefficients T evaluated for the tapers calculated for 1614 geometries (see text for details), (b) Evaluation of taper transmission for fine tuning of taper tip widths w2InP and w2Si around geometry #4 (see Table 2) with the highest transmission found in (a).
4. Conclusions
In this work, we focus on the numerical investigation of the heterogeneously integrated hybrid waveguide system developed on the silicon-on-insulator platform to demonstrate its capability when used as a scalable quantum on-chip photonic integrated circuit. The structure can be fabricated by standard photo- or electron-beam lithography techniques, utilizing a bonding step to join two wafers of different materials. One of the materials can be based on the III-V compound, e.g. InP, which allows for the fabrication of high-quality quantum dot emitters, using, e.g. InAs, and operating at the 1550 nm photon wavelength. Therefore, we studied the dipole coupling in the hybrid InP/Si waveguide, the mode structure depending on the cross-sectional geometry, the linear taper structure for efficient transfer of guided light from the InP/Si hybrid system to the Si waveguide, and the possible outcoupling to interconnect with the external detection system. First, we found that the dipole coupling to the InP/Si waveguide modes amounts to 38%. In addition, applying a reflector on one side of the waveguide or employing a chiral coupling effect can ensure unidirectional emission and the dipole coupling can reach up to 76%. This number can still be significantly increased using a quantum dot-in-cavity design, where the cavity is incorporated into the InP/Si waveguide, nonetheless, for the price of narrowing the spectral bandwidth of the device. Next, we found that the photon field transfer between the InP/Si waveguide and the Si waveguide reaches 87%. Therefore, the overall on-chip coupling, considering the light field transfer from an emitting dipole to the Si waveguide, can reach 33%. Again, this number is highly controlled by the dipole-waveguide directional coupling and can be increased at the cost of spectral narrowing of the device’s transmission bandwidth. However, we show that our conceptual device can operate in the broadband spectral range of 1.5-1.6 µm. It eliminates the problem of precise control over the quantum dot emission wavelength, which is critical for the cavity fabrication process. Finally, we investigated outcoupling efficiency realized by the circular Bragg grating-based system for the out-of-plane collection and by the spot size conversion for the in-plane collection. The results show the efficiency of the vertical outcoupling at the level of 26% and up to 10% of the in-plane outcoupling, both within NA of 0.65, and both showing broadband operability.
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