单片炉的设计及在快速热处理中的应用

A resistively heated, vacuum- and atmospheric-pressure-compatible, single-wafer furnace (SWF) system is designed to improve the operational flflexibility of conventional furnaces and the productivity of single-wafer rapid thermal processing (RTP) systems. The heat source design and system operation concepts are described. The temperature measurement/control techniques and thermal characteristics of the heat source are described. The heat transfer mechanism between the heat source and Si wafer is discussed. Temperature and process uniformity in SWF were demonstrated in TiSi formation, implant annealing and thin-oxide formation. The defect-generation phenomenon in Si wafers during atmospheric pressure RTP in a SWF system is investigated as a function of temperature, process time, wafer handling method and speed. Highly repeatable slip-free RTP results were achieved in 200-mm-diameter Si wafers processed at 1100◦C for 60 s (up to 5 times) through the optimization of the wafer handling method and speed.

Introduction Horizontal batch furnaces have been used in thermal processing applications such as dopant diffusion, annealing, oxidation, nitridation and thermal chemical vapor deposition (CVD) since the inception of semiconductor industry. Vertical batch furnaces were then introduced to improve the temperature uniformity and effificiency of clean room space usage. Both types of batch furnaces are widely used and able to meet the requirements for many thermal processing applications, even for 0.18µm gate technology.1) As device dimensions and allowable thermal budgets (more precisely, integral of diffusivity during thermal process) decrease, many thermal processing applications are coming to be performed in single-wafer rapid thermal processing (RTP) systems. The need for improved ambient control with the introduction of new materials requires a single-wafer processing system. Single-wafer RTP technology has signifificant advantages over thermal processing in conventional batch furnaces (150–200 wafers/batch) in terms of thermal budget reduction and process flflexibility improvement in temperature range and lot sizes.1) Typical furnace process times ranged from 4 to 6 h per batch. A high temperature process time could approach 10 h per batch. Typical ramp-up and rampdown rates in standard vertical furnaces are ∼10◦C/min and ∼3◦C/min, respectively.2) Typical process times in the RTP system are 1 to 5 min per wafer while the ramp-up and rampdown rates range from 20◦C/s to 250◦C/s. Rapid wafer temperature ramping-up and ramping-down renders the thermal process very effificient without increasing the thermal budget.3) A small temperature gradient on wafers heated above 1000◦C, however, can cause plastic deformations (crystalline slips) which strongly affect the device yield.4) Slip-free RTP of large-diameter (200 mm and larger) Si wafers is still a signifificant technical challenge.5)

Typical cold-wall-type RTP systems employ halogen lamps to heat wafers by optical interaction between light source (lamps) and wafers. The hot-wall-type RTP systems use a resistively heated susceptor as a heat source. Lamp-based RTP systems have very poor energy effificiency and require complicated temperature measurement/control algorithms to maintain within-wafer temperature uniformity during processing and minimize temperature overshooting or undershooting. Although susceptor-based RTP systems have higher energy effificiency, they can only be used in low-pressure (<100 Torr) non-oxidation environments due to the susceptor material (SiC-coated graphite), because of large heat loss from the susceptor to the water-cooled chamber wall through gas conduction as well as radiation.We have designed a single-wafer furnace (SWF) with a vacuum load lock to overcome the drawbacks of batch furnaces and single-wafer RTP systems.7, 8) In this paper, the design concept and thermal behavior of the heat source are described in detail. Theoretical calculation results on heat source confifigurations are discussed. Wafer temperature characterization results during ramping-up and rampingdown as well as typical process results using the heat source are described. The defect-generation phenomenon in 200-mm-diameter Si wafers during RTP in a SWF and the defect elimination method is discussed. Slip-free RTP process results are obtained by process parameter optimization.

Heat Source Design 

Designing a uniform heat source is the most important task in achieving repeatable and uniform process results without adjustments. In order to uniformly heat a large-diameter semiconductor wafer, a uniform planar heat source is desired rather than arrays of linear or point heat sources. However, the development of a large-area, planar-heating element is impractical from the view point of balancing physical properties such as electrical resistivity, thermal conductivity, thermal diffusivity, thermal mass, thermal expansion, material uniformity and manufacturability. Prior to designing the heat source, the geometrical effect of a heat source on a wafer is theoretically calculated. Calculation results were reflflected in the heat source design.

2.1 Heat transfer mechanism At low temperatures (<800◦C), heat transfer between a heat source and a heated object (Si wafer) is dominatedby conduction and convection. Heat transfer by convection is signifificant only if the ambient pressure is reasonably high and the heat source is placed at the bottom. As the heat source temperature increases, the radiation heat transfer (exchange) becomes dominant. Since the radiation heat exchange strongly depends on surface conditions (emissivity, reflflectivity, roughness etc.), geometries and orientations, the heating element must be appropriately confifigured to obtain reasonable temperature uniformity at high temperatures (>800◦C).

Fig. 1. Normalized view angle (a) and absolute view angle (b) on the plane at distance d = 10 mm from heating elements with diameters of 1, 5 and 10 mm (number of heating element = 11, pitch = 30 mm).