超薄单晶硅微结构

ABSTRACT

This paper discusses the fabrication of submicron p'microstructures for a number of MEMS applications using boronion implantation, rapid thermal annealing, and boron etch-stop. Toform these thin structures, the silicon is implanted with boron at anenergy of 40keV and doses of 5x10'cm’ and 7x10'scm whichproduce a peak concentration of more than 10cm, sufficient forachieving an effective etch-stop in EDP. The thickness of the p*layer varies from 0.2 to 0.3um depending on the annealing time andtemperature. A number of microstructures, including thin silicondiaphragms as large as 2mm on a side and 0.2um thick, hot wireanemometers with a TCR of -1600ppm/C, and piezoresistivesound detectors, have been fabricated with high reproducibility,uniformity, and yield.

INTRODUCTION 

 Operation of many physical sensors is based on thin  membranes or beams which deflect in response to an external  parameter. GeneraJly, the sensitivity of the sensor is strongly  dependent on the thickness of these microstructures. One common  technique for fabricating thin microstructures is based on hightemperature boron diffusion and boron etch-stop [l]. Forming  microstructures from p ++ silicon has been a powerful technique for  fabricating a variety of high-performance sensors [2]. This  technology offers several features, including the ability to form  single-crystalline silicon microstructures which possess reliable  and reproducible material properties, process simplicity, and  reproducibility. However, thermal diffusion limits the minimum  thickness of a p ++ film to >2-3µm due to the high temperature  process which is necessary to create a high boron concentration  (>9Xl0 19cm·') for achieving an effective etch-stop. The ability to  form submicron p ++ membranes is instrumental to many emerging  applications which require a wide dynamic range and high  sensitivity. This paper presents the fabrication of submicron p ++  microstructures using boron ion implantation and EDP etching.  Extensive simulation and experimental results are presented to  define the limits and capabilities of this process, and examples of  various devices fabricated using this technology are discussed.

FABRICATION PROCESS

The most critical step in the fabrication of submicron p'silicon microstructures is determining the most appropriate implantand annealing parameters, and choosing an appropriate etchant forachieving a reliable and uniform etch-stop. The etch-stopcharacteristics of boron-doped silicon in KOH and EDP as afunction of boron concentration have been studied andcharacterized by other researchers [3]. In order to achieve aneffective etch-stop, the ratio of the etch rates between undoped andhighly-doped silicon should be generally higher than 100. As aresult, for an effective boron etch-stop in EDP, the boronconcentration has to be >9x10'cm’ In order to obtain a thinmicrostructure, this region of high concentration has to be confinedto a narrow region, which is possible using ion implantation.

                                                                               Figure 1: Boron concentration profile after various annealing  temperatures and times.  

EXAMPLES  The above technology has been applied to fabricate a number  of devices, including thin silicon membranes for capacitive  pressure sensors, p .. silicon wires for flow sensors, and p ++ resistors for piezoresistive pressure sensors and sound detectors. Thin  membrane fabrication is performed in standard bulk  rnicromachining, while the silicon wires and piezoresistive sensors  are fabricated using the dissolved wafer process [5]. The  fabrication of each of these devices will be briefly described below.  To fabricate the ultra-thin silicon membranes, the front side  of a silicon wafer was first implanted with boron at 40keV at a  dose of 7xl0"cm·'. After implantation, the wafer is thinned down  to 200µm to reduce the EDP etch time. Note that EDP still etches  highly-doped silicon at a slow rate because the front side of the  wafer is exposed to the EDP etch during the entire etch period.  Next, the backside of the silicon wafer is covered with a 2000Alayer of PECVD nitride, which is deposited at a temperature of  400°C for 10 minutes. Low temperature dielectric deposition is important for obtaining thin p .. layers because high temperature  processes will drive the boron deeper into the silicon substrate and  lower the dopant concentration. The PECVD dielectric layer is  now patterned to create windows for the EDP etch, which etches  through the entire thickness of the wafer and stops on the p .. film.  Figure 2 shows a silicon membrane formed using EDP etching  following an RTA at 1000°C for 20sec. The diaphragm is buckled due to non-uniform stress distribution. This is easily corrected by  performing a second RT A at 1100°C for 30sec. after the EDP etch, as shown in Figure 3. The diaphragm thickness is about ~2000A  which is very close to the simulation result taking the finite etch  rate of highly-doped silicon into consideration.