Abstract
This study uses supercritical electroplating for the filling of through silicon vias (TSVs) in chips. The present study utilizes the inductively coupled plasma reactive ion etching (ICP RIE) process technique to etch the TSVs and discusses different supercritical-CO2 electroplating parameters, such as the supercritical pressure, the electroplating current density’s effect on the TSV Cu pillar filling time, the I–V curve, the electrical resistance and the hermeticity. In addition, the results for all the tests mentioned above have been compared to results from traditional electroplating techniques. For the testing, we will first discuss the hermeticity of the TSV Cu pillars, using a helium leaking test apparatus to assess the vacuum sealing of the fabricated TSV Cu pillars. In addition, this study also conducts tests for the electrical properties, which include the measurement of the electrical resistance of the TSV at both ends in the horizontal direction, followed by the passing of a high current (10A, due to probe limitations) to check if the TSV can withstand it without burnout. Finally, the TSV is cut in half in cross-section to observe the filling of Cu pillars by the supercritical electroplating and check for voids. The important characteristic of this study is the use of the supercritical electroplating process without the addition of any surfactants to aid the filling of the TSVs, but by taking advantage of the high permeability and low surface tension of supercritical fluids to achieve our goal. The results of this investigation point to a supercritical pressure of 2000 psi and a current density of 3Adm−2 giving off the best electroplating filling and hermeticity, while also being able to withstand a high current of 10A, with a relatively short electroplating time of 3 h (when compared to our own traditional dc electroplating).
Introduction
Electronic devices are in constant development and their needs always increasing: such is the need for light-weight devices, addition of more functions, faster processing speeds and less power consumption. To achieve these new specifications, the integrated circuit (IC) design of the components must become more and more complicated. We also know that the semiconductor industry is guided by Moore’s law, which states that the number of transistors in a device shall double while decreasing the cost by half every 18months [1], but the traditional fabrication methods for transistors are every day closer to their physical limitations.
Compared to the traditional 2D-plane wiring methods, 3D structures have the advantage of increasing effective wiring area of the chip and the fabrication technique focuses on a multi-layer approach, stacking layers in the vertical direction and increasing the connection density of the transistors. By utilizing this approach of multi-layered areas of the IC, we can reduce cost, packaging space, volume and weight. 3D ICs have the advantages of (1) a more dense IC design, (2) reducing the length of connections which increases the speed of signal transmission, (3) integrating together different fabrication processes and devices. We believe that due to the recent development of 3D ICs and their increased concentration, Moore’s law will continue to dictate the industry and that the key technology for 3D ICs is the through silicon via (TSV).
The commonly encountered TSV fabrication methods consist of traditional electrodeposition method, which uses electroplating of metal with addition of surfactants to fill the TSV and achieve a satisfactory result [2, 3]. But this kind of process will lead to a high impurity [4] content on the electrolyte and therefore on the TSV as well. Also, the TSV electroplating time using traditional method is much longer, because the electroplating solution cannot flow as easily into TSV micro-holes. Therefore, this study uses the new supercritical electroplating method to fabricate TSVs embedded on a chip. The term ‘supercritical’ denotes any fluid that surpasses its critical temperature and critical pressure values, at which point it will show properties in between that of a gas and a liquid and as such, has beneficial properties of both states of matter [5]. The special properties of supercritical fluids include low viscosity and low surface tension [6], therefore supercritical fluids can easily flow into TSV micro-holes, making the TSV structure fill in a more void-free fashion. While using the supercritical electroplating method, we can reduce the electroplating time and in this study different supercritical electroplating parameters are discussed and combined with MEMS fabrication processes to fabricate a TSV chip that effectively conducts electricity between layers.
In the present study we present and discuss electroplating of TSVs under different electroplating parameters and show that even without addition of any surfactants to aid the process, the electroplating solution can effectively flow into TSV micro-holes. The influence of changing the supercritical pressure and electroplating current density on the TSV fabrication is also discussed. In addition, TSV vacuum sealing, electric resistance, I–V curve and electroplating time needed by using supercritical electroplating and traditional electroplating techniques are also compared.
Fabrication process
Fabrication of the TSV chip
The TSV fabrication process is shown in figure 1; for this study a 4” monocrystalline Si wafer ((100) cut, 500μm thick, polished on one side) is used. First the surface of the wafer is cleaned through Piranha cleaning process (H2O2:H2SO4 = 1:4) while being heated at 110°C (for 20min). Next the surface is washed with acetone and isopropyl alcohol and finally soaked in plenty de-ionized (DI) water. A spin-coating process comes next to apply AZ4620 photoresist (PR) (25μm thick), followed by a photolithography process to define the position of the etch marks for the TSV holes on the surface. This is followed by inductively coupled plasma reactive ion etching (ICP RIE) to etch through-holes (diameter of hole: 70μm). Finally, the etched wafer will be cut with a wafer cutter into 2 × 2cm chips. The chips are then placed in an oxidation furnace to deposit a SiO2 insulation layer (200nm thick). The goal is not only to isolate the electrical signals, but also to prevent deposition from occurring at the side walls of the TSV during the supercritical electroplating process and to avoid the formation of voids; the electroplating process is done with bottom-up approach.
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