铜电解沉积技术

Copper electrodeposition in high-aspect-ratio through-holes micromachined by deep reactive ion etching is one of the most essential processes for fabricating through-wafer interconnects, which will be used in developing future generation high-speed, compact 3D microelectronic devices. Although copper electrodeposition is a well-established process, completely void-free electroplating in very deep and narrow through-holes remains a challenge, where local current distribution does not remain uniform, resulting in void formation in the via. In this paper, we report the fabrication of very high aspect ratio through-wafer copper interconnects by an innovative copper electroplating technique. Completely void-free electroplating in very deep  500  m and narrow through-holes was accomplished by a proposed “aspect-ratio-dependent electroplating technique.” In this technique, electroplating parameters were continuously varied along with changing unfifilled via depth. Continuously varying current density improves the local distribution of current as per the changing depth and helps in minimizing void formation. The hydrophilic nature of the via surface was also enhanced by wet surface treatment to improve the interaction between the copper electrolyte and via surface. Very fifine pitch  80  m , through-wafer copper interconnects having an aspect ratio as high as 15 were fabricated by the above innovative technique.

Through-wafer interconnect is one of the key technologies for fabricating next-generation compact 3D microelectronic devices. In this technology, several integrated circuit microelectromechanical system  IC/MEMS devices are interconnected in vertical axis by through-wafer vias fifilled with copper or other conductive materials. Compared to existing interconnect technologies, such as wire bonding, tape-automated bonding, and flflip chip, etc. through-wafer interconnects offer the shortest possible interconnect distance which results in the least parasitic losses, resistance-capacitance  RC delay, and flflight time and thus, the fastest possible response. They also offer several other advantages such as reduced packaging area, light weight, low cost, higher interconnection density, high reliability, excellent electrical performance with lower resistance, suitability for high-frequency applications, and device-scale packaging of microsystems.

From the satisfactory system performance and reliability point of view, completely void-free filling of conductive material in the through-holes is important. Voids or seams formed in the throughholes may cause serious reliability issues. At present, copper is used as an interconnect material due to its high electrical conductivity and higher electromigration resistance when compared to aluminum.3 In most cases copper is deposited by electroplating process,4-8 as it is able to deposit several hundred micrometer thick metal layers. Compared to other physical deposition processes like sputtering, E-beam evaporation, and chemical vapor deposition, CVD the electroplating process is cheaper, faster, and requires lower temperatures.

Although copper electroplating is a well-established process and its principles have been known for decades, completely void-free fifilling in very deep and narrow through-holes is still a challenging task. Previous research work in through-wafer electroplating is limited to aspect ratio in the order of 10.4 One of the major reasons behind the incomplete metal fifilling and void formation in high aspect-ratio through-wafer electroplating is the uneven local current density distribution at each point inside the through-holes. In highaspect-ratio   10 through-hole electroplating, current density does not remain uniform along the depth. At the entry and exit of via, current density is higher than that at the center. Due to higher current density, copper deposition rate is greater at the entrance and exit of vias. As a result of higher copper deposition at the entrance, vias are blocked at the top and bottom and a void is formed in the center.

Insuffificient wetting of through-hole side walls with copper electrolyte is also a possible reason behind void formation. In very deep and narrow through-holes, the electrolyte does not wet via surface completely and in some cases even does not reach all places.11 At present, deep and narrow through-holes in silicon are made by deep reactive ion etching DRIE . During the passivation step of the DRIE process, a thin layer of polymer is deposited on the sidewalls that protect it from lateral etching. This polymer pol tetraflfluoro compound is a hydrophobic material which prevents the wetting of the via surface with copper electrolyte. Due to insuffificient interaction between copper electrolyte and some local points on the via surface, current density distribution varies, which results in nonuniform copper deposition along the through-via surface. At some local points, copper deposition does not occur at all and voids are formed. In order to get completely void-free electroplating, the via surface is required to be properly wetted by copper electrolyte, which is not possible in narrow and deep through-holes where the vias opening size is in the order of a few micrometers.

In this paper, an innovative aspect-ratio-dependent copper electroplating technique is presented which is used to deposit copper in high-aspect-ratio through-holes of varying opening sizes and depths. Prior to the electroplating process, a surface treatment process was attempted to improve the hydrophilic nature of the via surface. Through-wafer copper interconnects with fifine pitch and aspect ratio as high as 15 are successfully fabricated by this technique.